Apple’s new M6 laptop/compute chip has continued the use of SoIC-MH advanced packaging, but high-end M-series chips (M6 Pro, Max, Ultra) may use 2 advanced packaging techniques, SoIC-MH for interconnect density and WMCM to integrate logic, LPDDR memory and high-speed I/O, media report, noting TSMC is readying capacity in 3 plants: Zhunan AP6, Longtan AP3 and Chiayi AP7. Analysts estimate WMCM capacity could reach 60,000 wafers-per-month (wpm) by end 2026 and over 120,000wpm in 2027. Important to note that the M6 is a monolithic die – everything on one slab of silicon – while the Pro, Max and Ultra versions are multi-die (chiplets) which need to be ‘stitched’ together via advanced packaging techniques.
SoIC-MH:…展开完整原文
Apple’s new M6 laptop/compute chip has continued the use of SoIC-MH advanced packaging, but high-end M-series chips (M6 Pro, Max, Ultra) may use 2 advanced packaging techniques, SoIC-MH for interconnect density and WMCM to integrate logic, LPDDR memory and high-speed I/O, media report, noting TSMC is readying capacity in 3 plants: Zhunan AP6, Longtan AP3 and Chiayi AP7. Analysts estimate WMCM capacity could reach 60,000 wafers-per-month (wpm) by end 2026 and over 120,000wpm in 2027. Important to note that the M6 is a monolithic die – everything on one slab of silicon – while the Pro, Max and Ultra versions are multi-die (chiplets) which need to be ‘stitched’ together via advanced packaging techniques.
SoIC-MH: System-on-Integrated-Chips Multi-Height
WMCM: Wafer-Level Multi-Chip Module $AAPL $TSM #semiconductors https://t.co/n7SCuuvFDF